1. Field of the Invention
The present invention relates to a semiconductor device having, on the same substrate, a p-channel MIS transistor and an n-channel MIS transistor in which the gate electrode structure is improved, and to a manufacturing method thereof.
2. Description of the Related Art
Recently, in silicon complementary metal oxide semiconductor (CMOS) devices, an attempt has been made to use, as a gate electrode, a high-melting-point metal such as titanium, molybdenum, tungsten or tantalum, or a nitride thereof. This is called the metal gate technique.
In the metal gate technique, depletion layers are not generated within the gate electrode in principle, and there is therefore no decrease in current drivability of a metal insulator semiconductor (MIS) transistor due to the depletion layers, in contrast with the case of a silicon gate. Particularly, in the so-called single metal gate technique in which a single metal gate material constitutes both gate electrodes of an n-channel MIS transistor and a p-channel MIS transistor, common deposition and processing of the gate electrodes of the n-channel MIS transistor and the p-channel MIS transistor are realized. This makes it possible to solve problems such as complication of a process and an increase in the number of steps which arise when different metal gates are used in the n-channel MIS transistor and the p-channel MIS transistor.
Materials such as TIN and TaN have heretofore been proposed as single metal gate materials. These materials have a work function ranging from 4.5 to 4.7 eV, and therefore permit threshold voltages of the n-channel MIS transistor and the p-channel MIS transistor to be set at the similar values with a single metal gate.
However, the single metal gate materials of this kind have a characteristic of taking on a polycrystalline structure regardless of composition and a film formation method. This has a considerable disadvantage on device characteristics. That is, the work functions of these materials are much dependent on crystal face orientation and fluctuate on a scale corresponding to crystal grain size in a polycrystalline thin film. Typical crystal grain sizes are about several tens to several hundreds of nm, and these dimensions are at about the same values as the gate lengths of future transistors. Therefore, when polycrystalline gate electrodes are used, the work functions of the gate electrodes fluctuate between transistors, and the threshold voltages also fluctuate. Since uniform performance is required in the transistors, this characteristic fluctuation is not allowable.
In order to solve this problem, it is necessary to use a monocrystalline metal gate or to adopt structural characteristics only having a fluctuation much smaller than the characteristic sizes (gate lengths) of the devices. Concerning the latter structure, an amorphous TaSiN metal gate electrode has been proposed (e.g., refer to D. G. Park et al., “Robust Ternary Metal Gate Electrodes for Dual Gate CMOS Devices”, 2001 IEDM, pp. 671 to 674). Amorphous substances have very high structural homogeneity and do not cause obvious characteristic fluctuation. However, the work function of the TaSiN metal gate is about 4.4 eV, and it has thus been impossible to use the TaSiN metal gate as the single metal gate.
Furthermore, a TaCx metal gate technique has been proposed in which a TaCx electrode is used for an n-channel MIS transistor (e.g., refer to J. K. Schaeffer et al., “Challenges for the Integration of Metal Gate Electrodes”, 2004 IEDM, p.p. 287 to 290). However, in this technique, the work function of the TaCx electrode is 4.18 eV, so that even if the TaCx electrode is used for the gate electrode of a p-channel MIS transistor, its threshold voltage becomes very high, and normal operation of the CMOS is impossible.
As has been described, it has been essential to replace the conventional silicon gate and introduce the metal gate technique in order to improve the current drivability of the transistor and realize a silicon CMOS device with a high processing speed. However, under the present circumstances, it is not possible to realize a single metal gate structure suitable to prevent the device characteristic fluctuation.
Thus, it is desired to realize a semiconductor device and a manufacturing method thereof which can realize the single metal gate structure suitable for use in, for example, silicon CMOS devices and which enable a decrease in the device characteristic fluctuation and attain higher reliability.